The present invention relates to a method for manufacturing a semiconductor device including metal interconnects, and more particularly to a method for manufacturing a semiconductor device including metal interconnects by using a dual damascene method.
In recent years, miniaturization and multilayering of interconnects have been advanced for the purpose of achieving higher packing densities of semiconductor devices.
Hereinafter, a known method of forming multilayer metal interconnects for a semiconductor device will be described with reference to the drawings.
FIGS. 7A through 7C, 8A, and 8B illustrate the known method for manufacturing a semiconductor device, wherein respective cross-sectional structures of part of multilayer interconnects including a via hole are shown in the order of process steps.
Initially, as shown in FIG. 7A, a first insulating film 101 and a second insulating film 102 each made of silicon oxide or the like are successively deposited on a semiconductor substrate (not shown). Subsequently, a lower-interconnect-forming groove is formed in a predetermined region of the second insulating film 102. A first barrier film 103 made of tantalum nitride and a second barrier film 104 made of tantalum are formed in the formed lower-interconnect-forming groove, and a lower interconnect 105 made of copper is then formed to fill in the lower-interconnect-forming groove with the first and second barrier films 103 and 104 interposed therebetween. Thereafter, a third insulating film 106 made of silicon nitride, a fourth insulating film 107 made of silicon oxide and a fifth insulating film 108 are successively deposited. Subsequently, an upper-interconnect-forming groove 108a is formed in a region of the fifth insulating film 108 above the lower interconnect 105. Then, a via hole 107a exposing the lower interconnect 105 is selectively formed in regions of the third and fourth insulating films 106 and 107 below the upper-interconnect-forming groove 108a. 
Next, as shown in FIG. 7B, a first barrier film 109 made of tantalum nitride and a second barrier film 110 made of tantalum are successively deposited on the fifth insulating film 108 over the whole area inclusive of the bottom surfaces and the sidewall surfaces of the via hole 107a and the upper-interconnect-forming groove 108a, by sputtering or the like.
Next, as shown in FIG. 7C, a plating seed layer 111 made of copper is deposited on the second barrier film 110 over the whole area inclusive of the bottom surfaces and the sidewall surfaces of the via hole 107a and the upper-interconnect-forming groove 108a, by sputtering or the like. Thereafter, as shown in FIG. 8A, an upper-interconnect-forming layer 112A made of copper is buried in the via hole 107a and the upper-interconnect-forming groove 108a by electroplating.
Next, as shown in FIG. 8B, part of the upper-interconnect-forming layer 112A deposited on the fifth insulating film 108 is removed by a chemical mechanical polishing method or the like, and the resultant upper surface is planarized, thereby forming an upper interconnect 112B and a via 112C from the upper-interconnect-forming layer 112A. Thereafter, a sixth insulating film 113 is deposited on the planarized fifth insulating film 108 and the upper interconnect 112B.
However, when miniaturization in the interconnect is further advanced, the known method for manufacturing a semiconductor device makes it difficult to bury the upper-interconnect-forming layer 112A in the via hole 107a by plating.
More particularly, the aspect ratio of the via hole 107a (the ratio of the depth to the aperture) becomes larger with miniaturization in the interconnect. Therefore, in each of the cases of depositing the first barrier film 109, the second barrier film 110 and the plating seed layer 111 on the via hole 107a, sputter atoms are required to have improved linearity (anisotropy).
On the other hand, when the linearity of the sputter atoms is increased, as shown in a sputtering step of FIG. 9A, every one of the first barrier film 109, the second barrier film 110 and the plating seed layer 111 is not sufficiently deposited on the lower part of the sidewall surface of the via hole 107a, resulting in these films and this layer being thinned. Especially, when the thickness of each of the first barrier film 109 and the second barrier film 110 is small, copper atoms constituting the plating seed layer 111 cohere so that the film to be formed may be non-uniform or discontinuous. Consequently, as shown in a plating step of FIG. 9B, the via hole 107a is not filled in with the upper-interconnect-forming layer 112A, and therefore a cavity-shaped defect called a void or a seam 107b is produced.
In this way, when the upper-interconnect-forming layer 112A is not surely buried in the via hole 107a, the resistance of each of the via 112C and interconnects 105 and 112B is increased, or electro-migration or stress migration occurs, resulting in significantly reduced reliability of the multilayer interconnects.
To cope with this, if the thickness of each of the first barrier film 109, the second barrier film 110 and the plating seed layer 111 is increased, as shown in a sputtering step of FIG. 10A, an overhang portion 111a formed at the upper end of the opening of the via hole 107a becomes larger. As a result, in a plating step of FIG. 10B, the almost whole internal part of the via hole 107a forms a seam 107c. 